Author: Avi Avanindra, Devardhi Mandya, Cypress
Network routers rely on statistical counters for performance monitoring, traffic management, and network security. These counters track the number of packets entering and leaving the network, as well as specific events like bad packet occurrences. Each incoming packet triggers updates to multiple counters, but the number of available counters and their update rate are often constrained by storage technology.
To manage these counters efficiently, high-performance memory is required to handle frequent read-modify-write operations. This article introduces a unique statistical counter solution that leverages the IP method. One end of the counter connects to a Network Processing Unit (NPU), while the other connects to a Xilinx QDR-IV memory controller. The QDR-IV Statistics Counter IP is a soft IP that uses QDR-IV SRAM to provide efficient statistical counting for network communication and other applications.
QDR-IV SRAM features two bidirectional data ports, A and B, which can perform two writes, two reads, or a combination in a single clock cycle. Each port supports DDR operation, with burst lengths of two words per cycle. The address bus is general-purpose, and both rising and falling edges provide addresses for Port A and Port B. Some versions include embedded ECC to enhance reliability and reduce soft errors.
There are two types of QDR-IV SRAM: HP (high performance) and XP (ultra high performance). HP operates at up to 667 MHz, while XP reaches 1066 MHz. XP improves performance by dividing memory into eight banks, using the three least significant bits of the address. This allows parallel access across different banks, maximizing throughput and reducing system costs.
The QDR-IV Statistical Counter IP is designed for use with QDR-IV SRAM and is ideal for network communication and other counter-based applications. It supports line cards up to 400 Gbps, with performance limited only by the FPGA and QDR-IV devices used. The IP connects to the NPU on one side and the QDR-IV memory controller on the other.
In operation, the IP handles statistical updates from the NPU and processes them through a PCIe interface. For example, an NPU might send 800 million STATS requests per second, each containing two counters (packet and byte counts) in a 72-bit word. These updates are stored in the QDR-IV SRAM and periodically written back to system memory.
The architecture includes components like SACOMP for address comparison, REQ_MXDMX for request handling, and ABCH_CTRL for managing read-modify-write operations. These ensure data consistency and efficient processing even under high load.
The QDR-IV interface uses 4:1/1:4 multiplexing for four channels, with specific mapping for HP and XP modes. In HP mode, requests are processed in order, while XP ensures no conflicts between ports by alternating odd and even addresses.
Overall, the QDR-IV Statistical Counter IP offers a scalable and reliable solution for managing large volumes of network traffic data efficiently.
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