Author: Avi Avanindra, Devardhi Mandya, Cypress
Network routers rely on statistical counters for performance monitoring, traffic management, and security. These counters track packet arrivals, departures, and specific events like bad packets. However, the number of counters and their update rates are often limited by storage technology.
To manage these counters efficiently, high-performance memory is essential to support read-modify-write operations. This article introduces a unique statistical counter IP that uses the QDR-IV SRAM. One end connects to a network processing unit (NPU), while the other connects to a Xilinx QDR-IV memory controller. The QDR-IV Statistics Counter IP offers efficient statistical counting for network communication and other applications.
QDR-IV SRAM features two bidirectional data ports, allowing two reads, two writes, or a mix in one clock cycle. Each port supports DDR operation, with a burst length of two words per cycle. The address bus provides separate addresses for each port, and some versions include embedded ECC for improved reliability.
There are two types of QDR-IV SRAM: HP (high performance) and XP (ultra high performance). HP operates up to 667 MHz, while XP reaches 1066 MHz. XP improves performance by dividing memory into eight banks, using the three least significant bits of the address. This allows access to different memory modules within the same cycle, enhancing RTR performance and reducing system costs.
The QDR-IV Statistical Counter IP is a soft IP that integrates with QDR-IV SRAM for network management and other counter applications. It supports line cards at 400 Gbps and faster, with performance limited only by the FPGA and QDR-IV devices used.
In operation, the NPU sends STATS update requests at 800M per second. Each request includes two counters (packet and byte counts) in a 72-bit word. The counter cache is updated to a lifetime counter in system memory every second via PCIe. The figure shows the setup of the STATS IP, QDR-IV memory, Xilinx controller, PCIe bus, and NPU.
The IP supports both HP and XP QDR-IV memories. Each counter stream uses a 72-bit word, and a 144Mb QDR-IV SRAM can store four million counters. The number of IP interfaces depends on the number of QDR-IV SRAMs used.
The NPU communicates with the IP over a 4x25 Gbps link. The IP runs at a quarter of the memory frequency and uses four parallel channels to match bandwidth. In HP mode, there are no address restrictions, but in XP mode, channels are assigned to odd and even addresses to avoid block limitations.
A processor readback request occurs every second, resetting memory locations. The architecture includes SACOMP for address comparison, REQ_MXDMX for request handling, and ABCH_CTRL for read-modify-write operations. These components ensure data consistency and efficient processing.
The QDR-IV interface uses 4:1/1:4 multiplexing/demultiplexing, with application channels mapped based on HP or XP mode. HP allows independent addressing, while XP ensures no overlapping accesses between ports. This design optimizes performance and reliability.
Overall, the QDR-IV Statistical Counter IP offers an efficient solution for managing network traffic and other counter-based applications.
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