The fundamental concept we will introduce today is called a "Timing Arc," which is the most essential element in timing analysis. In our previous discussion on library files, much of the timing-related information was presented through Timing Arcs. A Timing Arc represents a causal relationship between two pins in a circuit. It is primarily used to define either timing delays or timing checks. The term "Timing Arc" comes from the way it is visually represented in timing diagrams—often as a curved line. As shown in the figure below: Timing Arcs are defined at the cell level within the library, whereas there are no Timing Arcs between nets. Instead, the delay between nets is calculated based on RC parameters.
There are different types of Timing Arcs, categorized into two main groups: those that define timing delays and those that define timing checks.
**Timing Arcs for Delay:**
- Combinational Timing Arc
- Edge Timing Arc
- Preset and Clear Timing Arc
- Three-State Enable & Disable Timing Arc
**Timing Arcs for Checks:**
- Setup Timing Arc
- Hold Timing Arc
- Recovery Timing Arc
- Removal Timing Arc
- Width Timing Arc
Let’s start with the **Combinational Timing Arc**, which is the most basic type. If not specified otherwise, a Timing Arc falls into this category. It defines the delay from a specific input to a specific output, such as from A to Z. Combinational Timing Arcs can have three types of unate behavior: inverting (negative unate), non-inverting (positive unate), or non-unate. An inverting arc occurs when the output signal changes in the opposite direction of the input (e.g., input goes from 0 to 1, and output goes from 1 to 0). A non-inverting arc shows the same direction of change between input and output. A non-unate arc is when the output cannot be uniquely determined by the input alone.
Other Timing Arcs include:
- **Setup Timing Arc:** Defines the setup time required for sequential cells like flip-flops and latches, depending on whether the clock is rising or falling.
- **Hold Timing Arc:** Defines the hold time required for a timing component, also categorized based on the clock edge.
- **Edge Timing Arc:** Specifies the delay from the active clock edge to the data output, again divided into rising and falling edge cases.
- **Preset and Clear Timing Arc:** Defines the timing for when a clear or preset signal is applied, with four categories based on the signal edge and whether it's a preset or clear.
- **Recovery Timing Arc:** Specifies the minimum time a signal must remain stable before the next clock edge, depending on the clock's edge.
- **Removal Timing Arc:** Defines the minimum time a signal must stay stable after the clock edge, also categorized by the clock edge.
- **Three-State Enable & Disable Timing Arc:** Defines the delay from the enable signal to the output, split into two categories based on whether the enable is active or disabled.
- **Width Timing Arc:** Defines the minimum time a signal must remain at a particular logic level (either 0 or 1), categorized accordingly.
These Timing Arcs play a crucial role in static timing analysis (STA), ensuring that all signals meet their timing requirements across the entire design. Understanding them is key to analyzing and optimizing digital circuits effectively.
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