The fundamental concept we will be discussing today is the "Timing Arc," which is a core element in timing analysis. In our previous introduction to the library (lib), most of the timing-related information is represented through Timing Arcs. A Timing Arc is used to describe a causal relationship between two pins, and it is mainly categorized into two types: timing delay and timing check. The term "Timing Arc" comes from the way it is visually represented in timing diagrams—often as a curved line. As shown in the figure below, Timing Arcs are defined for cells within the library, while nets do not have Timing Arcs; instead, their delays are calculated using RC parameters.
There are several types of Timing Arcs that define timing delays:
- Combinational Timing Arc
- Edge Timing Arc
- Preset and Clear Timing Arc
- Three-State Enable & Disable Timing Arc
And for timing checks, there are also various types:
- Setup Timing Arc
- Hold Timing Arc
- Recovery Timing Arc
- Removal Timing Arc
- Width Timing Arc
Let’s start with the Combinational Timing Arc, which is the most basic type. If no specific category is mentioned, the Timing Arc is assumed to be combinational. It defines the delay from a specific input to a specific output, such as from A to Z. Combinational Timing Arcs can have three different "Sense" types: inverting (or negative unate), non-inverting (or positive unate), and non-unate. An inverting sense occurs when the output signal changes direction opposite to the input (e.g., input goes from 0 to 1, and output goes from 1 to 0). A non-inverting sense happens when both signals change in the same direction. A non-unate sense means the output cannot be uniquely determined by the input alone.
Other Timing Arcs include:
- **Setup Timing Arc**: Defines the setup time required for sequential cells like Flip-Flops or Latches, depending on whether the clock rises or falls.
- **Hold Timing Arc**: Defines the hold time needed after the clock edge.
- **Edge Timing Arc**: Describes the delay from the clock's active edge to the data output.
- **Preset and Clear Timing Arc**: Defines the timing for clearing data after a preset or clear signal, divided based on rising or falling edges.
- **Recovery Timing Arc**: Specifies the time before the clock edge during which the clear signal must remain stable.
- **Removal Timing Arc**: Specifies the time after the clock edge during which the clear signal must remain stable.
- **Three-State Enable & Disable Timing Arc**: Defines the delay from the enable signal to the output, depending on whether it is enabled or disabled.
- **Width Timing Arc**: Defines the minimum time a signal must stay at a particular level (either 0 or 1).
These Timing Arcs play a critical role in Static Timing Analysis (STA), helping ensure that all paths meet timing requirements and avoid violations. Each type serves a specific purpose in modeling the behavior of digital circuits under different conditions. Understanding these concepts is essential for accurate timing verification and design optimization.
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