Zedboard implements hardware and offline processing of algorithms

Abstract : This paper chooses a novel image scaling algorithm for FPGA hardware implementation. The algorithm is based on the idea of ​​parity decomposition, and has outstanding advantages such as low complexity, small hardware requirements and good scaling effect. Firstly, the algorithm is verified by MATLAB, and then the image processing effect based on the algorithm is evaluated by scaling time, PSNR, edge blur level and impulse noise. Compared with the traditional time domain algorithm, the comparison results show the superiority of the algorithm in processing effect and operation speed. Based on the Zedboard development board, the Vivado HLS advanced synthesis tool is used to integrate the algorithm C program into hardware IP, and a soft and hard co-verification system including ARM processor and VGA modules is built. The experiment verifies the correctness and practicability of the hardware design of the image scaling algorithm.

1 Introduction

Digital image processing has become a research hotspot because of its wide application in various fields of social life. Image scaling is a basic and critical operation in digital image processing. Most images and video frames are stored and transmitted in a compressed format to reduce the occupation of storage resources and improve the efficiency of data transmission. Users often require images of different resolutions for different applications. For example, in order to save bandwidth during image data transmission, it is usually necessary to transmit a low-resolution image, and when an image is received, it is desirable to see a high-resolution image when displaying. Despite the existence of various data compression software, the compression of data is still limited, and the compression of the data is likely to have caused some damage to the image, and does not ensure the retention of key information of the image. There are many image scaling algorithms, which can be divided into two types of algorithms based on time domain and frequency domain. In time domain image scaling methods, there are mainly nearest neighbor algorithm, bilinear interpolation algorithm and bicubic linear interpolation. Although they gradually increase the distortion after improving the image scaling process, its decreasing computing speed has become a problem that cannot be ignored (especially in video frame amplification, the switching frequency of the picture limits the executable time of the scaling algorithm) .

Some of these algorithms are implemented by high-level languages ​​such as MATLAB and C on a PC, some are based on embedded processors such as ARM, and others are based on FPGAs. Since PC and ARM are multi-tasking operating systems, scaling algorithms implemented by software programming is a common image scaling processing method. System code parsing and serial execution, as well as multi-tasking switching and other factors can seriously reduce image scaling efficiency and real-time data display. Frequent image scaling will impose a considerable burden on the normal operation of the system. Therefore, this paper focuses on the third image scaling implementation method, making full use of FPGA parallel computing, high integration, programmable and low-cost features, programming to achieve the hardware structure and IP generation of the scaling algorithm, in order to further realize the dedicated image scaling processing chip Development and application help to free up the processor and improve image quality and efficiency.

After considering the image processing effect, computing speed and hardware resource requirements, this paper selects the algorithm proposed by Hoon Yoo and Byong-Deok Choi [1] - Image scaling algorithm based on parity decomposition and segmentation weighted interpolation (WLI for short) Algorithm) for hardware implementation.

The WLI algorithm realizes the establishment of new point values ​​in images based on the 16 correlation points by means of the theory of parity decomposition. This topic is based on Xilinx's fully programmable device Zedboard. It uses the vivado hls advanced synthesis tool to write a synthesizable c program, realizes the hardware IP design of the WLI scaling algorithm, and verifies the high efficiency and low time of hardware scaling by using the actual scaling operation of the development board. The design was verified by consuming features and VGA contrast display experiments with image scaling. At the same time, the designed IP can also be used for SoC multiplexing of image processing, which reduces the difficulty of SoC development.

2. Image interpolation algorithm and MATLAB simulation 2.1. Traditional interpolation algorithm

In this paper, the simplest nearest neighbor interpolation algorithm based on four related points is selected; the bilinear interpolation algorithm with second-order linear operation is involved; and the bicubic interpolation operation of the most complex multi-floating operation is used as the comparison algorithm. An image quality and efficiency evaluation method to evaluate the pros and cons of the WLI algorithm (specific algorithm implementation reference [2] related content).

2.2. WLI algorithm

The WLI algorithm applies the idea of ​​parity decomposition to perform parity decomposition on the four points in the one-dimensional scaling (see Figure 1 for an example of the relationship between the odd and even partial correlation values). From the definition analysis, the odd part vector is a high-pass filter structure in the frequency domain image data processing, which has stronger noise than the even part vector. The influence of noise and high-frequency signals on this part tends to obscure the contribution of this part to the value of the correctly scaled pixel. Therefore, it is simple to avoid the damage caused by the noise and other parameters carried in the odd part vector. The linearization operation yields the processing scheme of equation (1).

Because of the symmetry of the even vector, it has a great influence on the final value of the zoom point. Although the direct linear fitting has the characteristics of simple operation, as shown in Figure 2, this will cause the picture point value to change too fast, affecting the visual effect. In order to make the value of this part have a slowly changing feature, the prototype equation based on the smooth curve is a good choice, but the resource consumption caused by the complex operation of the curve often makes the algorithm zoom out. Therefore, the citations of this part of the curve formula analysis and discussion, clever introduction of w parameters to complete the reduction and approximation of the operation method, as shown in Figure 2, the final is the same equation for the fit curve image interpolation calculation formula ( 2).

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