Introduction to the hardware architecture of smartphones

With the continuous development of the communication industry, mobile terminals have evolved from a single call function to voice, data, image, music and multimedia . For mobile terminals, there are basically two types: one is a traditional phone. The other is a smart phone. The smart phone has the basic functions of a traditional mobile phone and has the following features: open operating system, hardware and software scalability and support for third-party secondary development compared to traditional mobile phone smartphones. With its powerful functions and convenient operation, it has become more and more popular with people and will gradually become a trend in the market. However, as a portable and mobile terminal, it relies entirely on the battery to supply power. As the function of the smartphone becomes more and more powerful, its power loss is also increasing. Therefore, it is necessary to increase the usage time and standby time of the smartphone. There are two kinds of problems for this problem. Solution: One is equipped with a larger capacity mobile phone battery; the other is to improve the system design using advanced technology to reduce the power loss of the mobile phone.

At this stage, the battery equipped with mobile phones is mainly lithium-ion batteries. Although the energy density of lithium-ion batteries has increased by nearly 30% compared with the past, it still cannot meet the development needs of smartphones. The energy density of lithium-ion battery materials currently used is only about 20%. The boosting space and another fuel cell that is widely regarded by the industry as the future development trend of mobile phone batteries enables smartphones to talk for more than 13 hours of standby time for up to one month, but this battery technology is still immature. For a period of time [1] increasing the total battery capacity of mobile phones will increase the cost of the whole machine. Therefore, starting from the overall design of the smart phone, advanced technology and devices are used to reduce power loss and design the smartphone as much as possible. The use of time and standby time In fact, low-power design has become an increasingly pressing issue in smartphone design.

1 Smartphone hardware system architecture

The hardware architecture of the smartphone discussed in this article is using a dual CPU architecture as shown in Figure 1.

Low power loss design for smartphones

The main processor runs an open operating system and is responsible for the control of the entire system. The slave processor is a DBB (digital baseband chip) in the wireless Modem part, which mainly performs A/D conversion, D/A conversion, encoding and decoding of digital voice signals, and channel. The codec and the timing control of the wireless Modem part are communicated between the master and slave processors through the serial port. The main processor adopts the CPU chip of XXX company. It adopts CMOS technology and has ARM926EJ-S core. ARM AMBA (advanced microcontroller bus system) Structure) contains 16 kB instruction cache, 16 kB data cache and MMU (memory management unit). In order to realize real-time video conferencing function, an optimized MPEG4 hardware codec can be used for large-quantity MPEG4 codec and speech. Compression decompression for hardware processing to ease the computational pressure of the ARM core. The main processor includes an LCD (liquid crystal display) controller, a camera controller, a SDRAM and a SROM controller, many general-purpose GPIO ports, an SD card interface, etc. Can be used very well in the design of smartphones

In the hardware architecture of the smart phone, the wireless modem part only needs to add certain peripheral circuits such as audio chip, LCD, camera controller, microphone, speaker, power amplifier, antenna, etc. It is a complete hardware circuit simulation of a normal mobile phone (traditional mobile phone). The baseband (ABB) voice signal pin and the audio codec chip communicate to form a voice channel during the call

From the system architecture of this hardware circuit, it can be seen that the most power-consuming part includes the main processor, wireless modem, LCD and keyboard backlight, audio codec and power amplifier. So how to reduce their power consumption in the design is a very Important issues

2 low power design

2.1 Reduce the supply voltage and frequency of the CPU part

In the digital integrated circuit design, the static power consumption of the CMOS circuit is very low compared with its dynamic power consumption, and the dynamic power calculation formula is not considered.

Pd=CTV2f (1)

Where: Pd is the dynamic power consumption of the CMOS chip; CT is the load capacitance of the CMOS chip; V is the operating voltage of the CMOS chip; f is the operating frequency of the CMOS chip

It can be seen from equation (1) that the power consumption in the CMOS circuit is linear with the switching frequency of the circuit and the supply voltage is quadratic. For the CPU, the higher the Vcore voltage, the faster the clock frequency and the greater the power consumption, so it can be satisfied normally. Under the premise of system performance, the CPU with low voltage operation should be selected as much as possible. For the selected CPU, lowering the supply voltage and operating frequency can achieve better results in overall power consumption.

For the main CPU, the core supply voltage is 1.3 V, which is very small and its main frequency can be set at full speed. The other various frequencies required internally are generated by the main frequency division to generate the main CPU frequency fCPU. Calculated as follows:

Calculation formula

In order to prevent static electricity from being damaged on the COMS chip, the unused pins cannot be suspended. Generally, the pull-down resistor is connected to reduce the input impedance. The drain path needs to be added to increase the output level to improve the noise margin of the chip input signal to enhance the anti-interference. Capabilities, but the following points must be considered when selecting pull-up resistors:

a) Considering that the pull-up resistor should be large enough to reduce the current in terms of power consumption and chip sink current capability;

b) that the pull-up resistor should be small enough to increase the current from ensuring sufficient drive current;

c) Excessive pull-up resistors in high-speed circuits can make signal edges flat and signal integrity will deteriorate

Therefore, in consideration of the ability to properly drive the latter stage (ie, consider the chip's VIH or VIL), try to select a larger resistance value to save the system's power consumption.

2.2 DPM

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