Application Research of Image Enhancement Algorithm Based on FPGA Acquisition Card

0 Preface

In the process of acquisition, the image will inevitably be affected by factors such as sensor sensitivity, noise interference and quantization problems during analog-to-digital conversion, resulting in the image not meeting the visual effect of the human eye. For the purpose of human eye observation or automatic machine analysis, the original The improved behavior of the image is called image enhancement technology. Therefore, image enhancement technology is a general method to improve image quality, but it is also targeted. It must be a specific algorithm for a specific need to achieve image quality improvement.

Image enhancement technology generates a variety of algorithms according to various purposes. According to different processing spaces, these algorithms are divided into spatial domain-based image enhancement algorithms and transform domain-based image enhancement algorithms. The image enhancement algorithm based on spatial domain can be divided into spatial domain transform enhancement algorithm, spatial domain filter enhancement algorithm and spatial domain color enhancement algorithm. Image domain enhancement algorithm based on transform domain can be divided into frequency domain smoothing enhancement algorithm and frequency domain sharpening. Enhanced algorithms and frequency domain color enhancement algorithms.

This paper adopts the spatial domain image enhancement algorithm, which mainly uses a certain image gray value mapping criterion to adjust the dynamic range of image gray scale, thus achieving image enhancement.

1 image acquisition card overall structure

As shown in Figure 1, the entire capture card can be divided into three sub-modules, mainly including a PCI bus portion, an FPGA system portion, and a peripheral interface portion. The main function of the PCI bus part is to complete the communication between the PC and the device on the PCI local bus, including PCI bus communication, bus arbitration on the local bus, data transmission, interrupt, interrupt handshake and configuration function of PCI9054 chip.

System Block Diagram

The FPGA system part mainly implements an FPGA minimum system. As a device on the PCI9054 local bus, the FPGA needs to communicate with the PCI9054 local bus interface. The same FPGA also needs to have the function of power-on automatic configuration. The peripheral interface section primarily communicates with the FPGA. Although various control signals are generated by the FPGA, these signals can be used for actual control after being converted. The main task of the peripheral interface part is to perform level shifting to meet the requirements of practical applications.

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